1. Field of the Invention
The present invention relates to an erase method in a flash memory device by which over-erase of the flash memory device is prevented.
2. Discussion of the Related Art
An exemplary device among various semiconductor memory devices is a non-volatile memory device. A user programs the non-volatile memory device by switching a memory state in an electrical manner. The non-volatile memory device is capable of sustaining its memory state even if power is shut down. Non-volatile memory devices are classified into a floating gate series and an MIS (metal-insulator-semiconductor) series having at least two kinds of stacked dielectric layers.
The floating gate series non-volatile memory device implements its memory characteristics using a potential well. The ETOX (RPOM tunnel oxide) structure used as flash EEPROM (electrically erasable & programmable read only memory) is a representative one thereof. The MIS series non-volatile memory device performs its memory function using traps existing in a dielectric layer, a bulk, a dielectric-to-dielectric interface, and a dielectric-to-semiconductor interface.
A typical structure of the floating gate series non-volatile memory device and program and erase methods using the same are explained with reference to the drawings as follows.
FIG. 1 is a cross-sectional diagram of an ETOX memory device as the floating gate series non-volatile memory device according to a related art.
Referring to FIG. 1, a tunnel oxide layer 102, a floating gate 103, a dielectric layer 104, and a control gate 105 are sequentially stacked on a p type semiconductor substrate 101. A source region S and a drain region D are formed in the substrate below both sides of the stacked structure, respectively. The dielectric layer 104 is generally formed of an ONO (oxide-nitride-oxide) layer to raise a coupling ratio.
Program and erase methods of the above-configured floating gate series non-volatile memory device are performed in the following manner. In the program method, electrons are injected in a potential well formed in a floating gate by hot electron injection or F-N (Fowler-Nordheim) tunneling to raise threshold voltage.
In the erase method, holes are injected by hot hole injection to recombine the holes and electrons or the electrons are drained out to a substrate to lower the threshold voltage.
In performing the erase process using the floating gate series non-volatile memory device according to the related art, a problem of over-erasing may take place. Over-erasing occurs when electrons stored in the floating gate are excessively drained, making the threshold voltage negative. Even if only one over-erased cell exists on a bit line in a non-volatile memory device circuit, over-current flows in the bit line, causing failures in reading data of other cells which are not over-erased.
FIG. 2 is a graph of memory cell number distribution to a threshold voltage in performing program and erase processes using a floating gate series non-volatile memory device according to a related art. Program and erase states having prescribed voltage distributions are shown in which each voltage of the program and erase states indicates a threshold voltage (VT) window W.
Referring to FIG. 2, there exists a cell ‘a’ for which the threshold voltage is below 0V due to over-erasing. A threshold voltage distribution in erase is thus wider than that in program. Once the threshold voltage distribution in erase is widened, a threshold voltage window W between the program and erase states is shortened, degrading characteristics of the flash memory device.
There are various reasons that may cause over-erasing, such as a line width in an active area, a tunnel oxide layer thickness, a junction overlap, a damaged tunnel oxide, local thinning of the tunnel oxide layer, pin holes, and the like. As there are various reasons that cause over-erasing, the related art method raises the threshold voltage of an over-erased cell to reprogram the corresponding cell, instead of fixing the root cause of the over-erasing. In the related art reprogramming method, the corresponding test time is too long and an additional circuit for restoring the over-erased cell is needed.